Elias realized this wasn't a standard programmer. It was a Trojan horse. Someone had used the J-Link's trusted position in the development chain to inject code directly into the silicon of every device it touched.
Disclaimer: This article is for educational purposes only. The author does not provide or distribute schematics for Segger products. All trademarks are property of their respective owners. jlink v9 schematic
Suddenly, the serial console on his laptop pinged. CPU: ARM Cortex-M3 r2p0 Found 1 JTAG device, Total IRLen = 4 Elias realized this wasn't a standard programmer
The is built around the high-performance STM32F205RCT6 jlink v9 schematic
At the heart of almost every J-Link (from V7 to V9) lies an NXP LPC microcontroller. This is the "Meta" layer of the probe—it’s a microcontroller debugging other microcontrollers.