161: Kuzuv0

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The rapid proliferation of computer‑vision workloads at the network edge demands hardware that can deliver high inference throughput while respecting strict power, area, and latency budgets. This paper presents , a custom‑designed, low‑power accelerator targeting vision‑centric deep‑neural‑network (DNN) inference on edge devices. KUZU‑V0‑161 combines a heterogeneous compute fabric (8× 8‑bit systolic MAC arrays, a 16‑bit tensor‑core, and a programmable SIMD engine) with a hierarchical memory subsystem optimized for data reuse. Leveraging a novel Weight‑Stationary‑with‑Dynamic‑Activation‑Reuse (WS‑DAR) scheduling policy, the accelerator achieves up to 2.9× higher energy‑efficiency than state‑of‑the‑art commercial microcontrollers on benchmark suites (ImageNet‑1K, COCO, and a custom traffic‑sign detection dataset). Silicon measurements from a 65 nm prototype demonstrate a peak performance of 1.6 TOPS/W at 0.55 V , a die area of 12 mm² , and a latency of 3.2 ms for a 224×224 ResNet‑18 inference. The paper details the architectural choices, the compiler pipeline, the micro‑architectural optimizations, and the experimental methodology, and discusses the broader implications for ubiquitous edge AI. This article aims to provide a comprehensive exploration

, is often featured in "silent reviews" and social media demonstrations.